Designed and manufactured two UAVs to compete in Raytheon Autonomous Vehicle Competition Operation Full Send.
One UAV scans and identifies markers within a field, while the other UAV delivers a package to one of the identified markers.
Led a team of 5 members to design a system to communicate navigation coordinates, status, and logs over WiFi and RF between two UAVs.
AES-128 Cryptographic Accelerator GWU ECE 6214
Spring 2025
Implemented a complete AES-128 encryption core using Verilog for secure, hardware-accelerated data processing.
Executed the physical design flow utilizing Cadence Innovus for precise chip layout, placement, and routing.
Optimized the synthesized logic to achieve an ideal balance between physical die area and processing speed.
USB Art-Net DMX Controller Personal Project
Summer 2026
Designed and routed a custom PCB, integrating an ESP32-S2 microcontroller with isolated DC-DC power and XLR3 DMX connectivity.
Developed embedded C firmware using the ESP-IDF framework to implement Art-Net/DMX communication protocols and a USB NCM interface for data routing.
32-Channel Digital Audio Mixer Personal Project
Summer 2026 (In Progress)
Architecting a custom 32-channel digital audio mixer targeting live theater applications.
Designing a mixed-signal PCB integrating ADC/DAC stages, power management, and an ESP32-S3 microcontroller.
Developing a TDM audio processing pipeline and SPI communication interface in SystemVerilog for a Cmod-A7 FPGA.
Writing C++ firmware to manage system routing and the user interface.
FPGA Ethernet Data Compression Pipeline UPenn ESE 5320
Fall 2025
Engineered a high-throughput Ethernet data compression system on an Ultra96 FPGA board, achieving processing speeds of 100Mb/s.
Developed the system architecture in C++ utilizing High-Level Synthesis (HLS) to leverage FPGA acceleration, parallel processing, and extensive pipelining.
Designed a comprehensive data processing pipeline featuring Content-Defined Chunking (CDC), SHA Hashing, Data Deduplication, and LZW Compression.
IoT Smart Chicken Coop UPenn ESE 5160
Spring 2026
Developed an automated, WiFi-connected environmental control system using an SiWg917 network processor.
Engineered a fully custom PCB to route electrical components and integrate temperature, humidity, air pressure, ambient light, and PIR motion sensors.
Programmed custom logic to autonomously trigger door actuators and feeders based on configurable environmental metrics and remote manual inputs.
8-Bit Pipeline ADC UPenn ESE 6680
Spring 2026
Designed an 8-bit Pipeline Analog-to-Digital Converter (ADC) capable of operating at a >2MHz sampling frequency using Cadence Virtuoso and an AMI 0.6ยต process.
Engineered Switched-Capacitor Multiplying DAC (MDAC) circuits for residue amplification and implemented sub-DACs utilizing resistive elements.
Characterized static (INL/DNL) and dynamic (SNDR, SFDR, ENOB) performance, optimizing for minimal power dissipation to maximize the Figure of Merit (FOM).
RV32IM Pipelined Processor UPenn CIS 5710
Spring 2026
Developed a fully functional RISC-V processor in SystemVerilog, successfully implementing the complete RV32IM Instruction Set Architecture (ISA).
Architected and integrated a classic 5-stage instruction pipeline to optimize instruction throughput and overall processor efficiency.
Developed an interactive shell supporting multi-process pipelines, standard I/O redirection, and foreground/background job control using process group isolation.
Engineered a FAT16-like file system within a single host file, implementing FAT chain traversal, block allocation, and a kernel-level open file table.
Architecting a priority-based process scheduler and kernel-level system calls to manage context switching, file descriptors, and process states.
Biometric Attendance System UPenn ESE 5190
Fall 2025
Engineered an automated classroom attendance tracking system utilizing an ATmega328PB microcontroller, a fingerprint sensor, and an LCD interface.
Collaborated in a 3-person team to develop secure biometric check-in/out functionality, streamlining the daily recording process.
Implemented data logging capabilities to securely store and append student ID records directly onto an SD card for instructor access.
SPI Memory Controller GWU ECE 6213
Fall 2024
Authored a Serial Peripheral Interface (SPI) controlled memory module in Verilog.
Designed the digital interface to successfully decode incoming SPI signals from a host microcontroller for reliable word storage and retrieval.